This invention is in the field of integrated circuits, and is more specifically directed to phase-locked loop circuits.
As is fundamental in the art, many modern electronic systems include numerous integrated circuits that operate in conjunction with one another. For example, consumer-oriented systems such as televisions and home theaters include video decoders for decoding an input video signal into digital video output signals that are synchronized with a synchronization pulse contained within the incoming video signal itself. Modern spread-spectrum communications transmitters and receivers require the generation of high-frequency clock signals for the modulation and demodulation, respectively, of signals over the multiple subchannels of the spread spectrum bandwidth. In these and other electronic systems, the generation of periodic signals for clocking the operation of circuit functions based upon a system clock or synchronization pulse, is a common and often critical function.
A conventional approach for generating periodic signals based upon a reference clock utilizes the well-known phase-locked loop (“PLL”). In general, PLL circuits operate by comparing the time at which an edge of a reference clock is received with a corresponding edge of an internally generated clock. If a significant delay between these two edges is detected, the generation of the internal clock is adjusted to more closely match the received reference clock. In conventional analog PLLs, the frequency of a voltage controlled oscillator is adjusted by a filtered signal from a phase detector that compares system and chip clocks, so that the instantaneous frequency of the internal chip clock is advanced or retarded depending upon whether the chip clock lags or leads the system clock. Analog PLLs adjust the phase of the chip clock in a substantially continuous manner in response to a phase difference between the internal chip clock and the system clock. This smooth operation generally depends upon the filtering of the output of the phase detector circuit, but can be made quite well-behaved in many implementations. Additionally, by inserting frequency dividers in the forward and feedback loops, analog PLLs can be used to generate periodic signals of a selectable frequency multiple of the input reference clock.
Several types of digital PLLs (DPLLs), in which some of the signals communicated around the loop are in digital form, are known in the art. A specific class of DPLL is the so-called “all-digital” PLL (ADPLL), in which all signals in the loop are digital. Known implementations of ADPLLs include divide-by-N counters, increment-decrement (ID) counters, and digital waveform synthesizers. Several conventional ADPLL designs are described in Best, Phase-Locked Loops: Design, Simulation, and Applications (McGraw-Hill, 1997), pp. 177-199.
By way of further background, clock generator circuits based on a phase-locked loop (PLL) are described in Mair and Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Solid State Circ., Vo. 35, No. 16 (IEEE, June, 2000), pp. 835-46, and in U.S. Pat. No. 6,329,850 B1, issued Dec. 11, 2001 and commonly assigned herewith, both documents incorporated herein by this reference. In these “flying-adder” clock generation circuits, the voltage controlled oscillator (VCO) of the PLL produces a plurality of evenly-spaced output phases at a frequency that is locked to a reference clock. A register stores a digital value that selects the desired phase to be applied to the clock input of a toggle flip-flop from which the output clock is generated. A frequency synthesis circuit adds integer and fraction portions of an incoming frequency selection value to the current contents of the register. The fraction portion of the frequency selection value permits a time-averaged clock frequency to be produced with more precision than would be attained by the integer portions selecting the multiple VCO output phases. This article and U.S. patent also describe alternative realizations, including multiple frequency synthesis circuits based upon the same PLL and the generation of a phase-shifted secondary output from a phase synthesis circuit that is slaved to the frequency synthesis circuit. Additional performance is obtained by providing separate paths for producing the leading and trailing edges of the output clock.
By way of further background, U.S. patent application Publication No. US 2003/0118142A1, published Jun. 26, 2003, from copending and commonly assigned application Ser. No. 10/026,489, filed Dec. 24, 2001, and incorporated herein by this reference, describes another flying-adder clock generation circuit, based on the flying-adder architecture of the Mair and Xiu article and U.S. Pat. No. 6,329,850 B1. In particular, this copending application describes a clock generation circuit in which two or more frequency synthesis paths terminate at the inputs of a multiplexer, the output of which toggles a toggle mode bistable multivibrator (T flip-flop). Sequential selection of the synthesis paths is controlled in a synchronized manner with the output of the circuit, so that the synthesis path outputs sequentially toggle the flip-flop. In this way, the number of synthesis paths can be increased arbitrarily, with the scaling limited by the performance of control circuits for the output multiplexer. The propagation delay paths of each synthesis path can then extend to the multiple periods of the output clock, making higher output frequency possible. In addition, the toggle signal operates as a double-frequency clock signal.
By way of further background, U.S. patent application Publication No. US 2004/0008805 A, published Jan. 15, 2004, from copending and commonly assigned application Ser. No. 10/376,453, filed Feb. 26, 2003, and incorporated herein by this reference, describes a phase-locked loop using a flying-adder frequency synthesizer, in which a central processing unit generates a feedback divide integer in the feedback loop from the VCO output (which provides the multiple phases to the flying-adder). Because the CPU generates the feedback ratio, the flying-adder frequency synthesizer can be designed to use only integer values, effectively eliminating jitter while still providing low frequency error.
By way of further background, we have previously used a flying-adder frequency synthesizer in an all digital phase-locked loop (ADPLL) architecture, to great advantage. An example of a product incorporating such an ADPLL is the TVP5145 video decoder, manufactured and sold by Texas Instruments Incorporated. FIG. 1 illustrates, in block form, conventional video decoder 2 constructed in this manner.
Conventional video decoder 2 receives analog video signals (in this case, red, green, and blue component analog signals R, G, B, respectively), and converts these analog signals into digital signals that can be readily displayed by a modern digital video display, in the form of a cathode-ray tube (CRT), a liquid-crystal display (LCD), a projection unit utilizing DIGITAL LIGHT PROCESSING (DLP) technology and devices available from Texas Instruments, or the like. Red analog video component signal R is received by analog-to-digital converter (ADC) 4A, green analog video component signal G is received by ADC 4B, and blue analog video component signal B is received by ADC 4C. Each of ADCs 4 are conventional analog-to-digital converter circuits, and are for sampling their respective input analog signal and presenting a digital output signal corresponding to the amplitude of the sampled analog signal. Accordingly, each of ADCs 4 are clocked circuits, with pixel clock signal PIX_CLK defining the times at which ADCs 4 sample their respective inputs. As evident by its name and its function in defining the sample times, pixel clock signal PIX_CLK corresponds to the pixel rate of the video display, each period corresponding to a pixel of the display.
Conventional video decoder 2 also includes data format manager 6, which receives the sampled digital signals from ADCs 4 for the color components of the video signal, and processes and arranges these component signals as desired for the destination display. Data format manager 6 thus includes such functions as digital filtering of the signals, automatic gain control (AGC), and the like; alternatively, if the input video signal is a composite analog signal, sampled by a corresponding ADC, data format manager 6 may also include such other functions as luminance and chrominance separation. Digital display device interface 8 receives the processed digital video signals from data format manager 6, and performs the appropriate interfacing functions to apply the decoded digital video signals to the appropriate digital display device.
In this conventional architecture, all-digital phase-locked-loop (ADPLL) 10 generates pixel clock signal PIX_CLK from clock signal HYSNC, which is the reference to which pixel clock signal PIX_CLK is to be locked by ADPLL 10. Clock signal HSYNC corresponds to the horizontal sync pulse in conventional analog video signals, and which is used to synchronize each display line in the eventually display of the image. Video decoder 2 may include a detector circuit for detecting the horizontal sync pulse in the composite signal and generating clock signal HSYNC, or alternatively clock signal HSYNC may be present in the input signal or generated elsewhere. In any case, in this video decoder implementation, ADPLL 10 receives clock signal HSYNC and generates pixel clock PIX_CLK based on that signal.
As typical in conventional video decoders, video decoder 2 also includes digital processor 11, which is preferably a programmable logic device such as a microprocessor, microcontroller, digital signal processor (DSP), or the like, and which manages the operation of video decoder 2.
Referring now to FIG. 2, the construction of ADPLL 10 as used in conventional video decoder 2, for example corresponding to the TVP 5145 video decoder available from Texas Instruments Incorporated, will now be described. ADPLL 10 is arranged as a loop that includes the fundamental functions of a phase detector, loop filter, controllable oscillator, and frequency divider, but the signals traveling this loop are all in the digital domain, as reflected in the “all-digital” nomenclature of ADPLL 10.
In conventional ADPLL 10, digital phase detector 12 includes a latch, clocked by clock signal HSYNC, and which generates digital phase error word PH_ERR and forwards this word to digital low-pass loop filter 14. The data input of digital phase detector 12 receives a pixel count value PIX_CNT from counter/frequency divider 18. Counter/frequency divider 18 is a binary counter that increments pixel count value PIX_CNT with each cycle of pixel clock signal PIX_CLK from zero toward a maximum pixel value max_pix−1, and then restarts from zero with the next cycle of pixel clock signal PIX_CLK. The maximum pixel count max_pix−1 preferably corresponds to the number of pixels in a display line (i.e., the value max_pix is the number of pixels per line). A frequency divider function in counter/frequency divider 18 may also divide the frequency of pixel clock signal PIX_CLK to produce another output clock signal OUT_CLK.
Upon digital phase detector 12 receiving an edge of clock signal HSYNC, digital phase detector 12 latches the current value of digital signal PIX_CNT from counter/frequency divider 18. Digital phase detector 12 calculates phase error word PH_ERR from this latched value of PIX_CNT. The range of phase error word PH_ERR is centered over ±π radians, by simple program code:
            if      ⁢                          ⁢      pix_cnt        <          (              max_pix        2            )            ph_err    =          pix_cnt      +              1        ⁢                                  ⁢        else                  ph_err    =          pix_cnt      -      max_pix      where pix_cnt is the latched value of digital signal PIX_CNT, and where ph_err is the value of digital word PH_ERR being generated in this iteration. A digital phase error value ph_err of zero, corresponding to true phase-lock, is unstable because this value corresponds to an error between maximum count value max_pix−1 and +1 (0 being between these values). These calculations therefore ensure that the value ph_err will never equal zero, because the value of pix_cnt can never equal −1 (resulting in ph_err=0), nor can it equal the value max_pix (because counter 18 wraps around at max_pix−1), thus avoiding the “dead zone” of ph_err=0. Phase error digital signal PH_ERR is centered around a value of 0 phase error, having a range of ±π.
When pixel clock signal PIX_CLK is synchronized with reference signal HSYNC, phase error value PH_ERR will remain substantially constant. In addition, to the extent that phase shifts in the reference signal HSYNC occur, the output of digital phase detector 12 is substantially linear.
The digital phase error word PH_ERR is then applied to digital low-pass loop filter 14. As known in the PLL art, a loop filter is important in ensuring phase-locking of the circuit, by reducing the sensitivity of the loop to small and rapid changes in phase difference. According to the preferred embodiment of the invention, loop filter 14 is a digital filter. Preferably, loop filter 14 is implemented in software, as a program sequence executed by digital processor 11 (FIG. 1) or other circuitry operating in or with ADPLL 10.
In general, digital low-pass loop filter 14 filters the values of phase error word PH_ERR to produce frequency control word FREQ, which in turn is applied to digital control oscillator (DCO) 15 according to this embodiment of the invention. Frequency control word FREQ indicates the frequency at which DCO 15 is to generate its output clock signal, preferably as a floating-point (integer plus fraction) multiple of a reference frequency based on a reference clock signal REF_CLK generated by oscillator 16 and applied to DCO 15. Pixel clock signal PIX_CLK is defined by the frequency selected by frequency control word FREQ.
By way of further background, referring now to FIG. 3, the construction of DCO 15, as implemented in conventional video decoder 2 corresponding to the TVP 5145 video decoder available from Texas Instruments Incorporated, will now be described. In summary, DCO 15 includes a conventional PLL 20 (which may be an analog or digital PLL), which produces multiple phases of a clock signal that is based on and locked to reference clock signal REF_CLK. These output phases are applied to flying-adder frequency and phase synthesizer 52, which also receives frequency control word FREQ from loop filter 14, and generates pixel clock signal PIX_CLK.
In the example of DCO 15 shown in FIG. 3, PLL 20 is a conventional analog PLL, including phase-frequency detector (PFD) 22 receiving reference clock REF_CLK and a feedback clock from divider 28. The output of PFD 22, which is typically a pulse having a width corresponding to the phase difference between the reference and feedback clocks, controls charge pump 26 to raise or lower its output voltage, depending on the polarity of the phase difference and its duration. The output of charge pump 26, filtered by low-pass filter 26, is applied to voltage-controlled oscillator (VCO) 30 as the control voltage. VCO 30 generates multiple phases of an output clock signal, locked in frequency to reference clock REF_CLK. These multiple clock phases are applied to flying-adder frequency synthesis circuit 52 for the generation of pixel clock PIX_CLK, and one of these phases is applied to frequency divider 28, from which the feedback clock applied to PFD 22 is generated.
In this example, VCO 30 generates thirty-two clock phases, at a frequency corresponding to that of reference clock REF_CLK. The time between successive phases at the output of VCO 30 determines the resolution at which APDLL 10 generates pixel clock signal PIX_CLK. For example, reference clock REF_CLK may be generated by a conventional crystal-based oscillator 16 at a frequency of 14.31818 MHz, divided down by a factor of eight. Adjacent clock phases based on this reference clock signal are therefore spaced apart by 0.282 nsec.
Detailed description of the construction and operation of flying-adder synthesis circuit 52 may be found in Mair and Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Solid State Circ., Vo. 35, No. 16 (IEEE, June, 2000), pp. 835-46; U.S. Pat. No. 6,329,850 B1, issued Dec. 11, 2001 and commonly assigned herewith; U.S. patent application Publication No. US 2003/0118142A1, published Jun. 26, 2003, from copending and commonly assigned application Ser. No. 10/026,489, filed Dec. 24, 2001; and U.S. patent application Publication No. US 2004/0008805 A, published Jan. 15, 2004, from copending and commonly assigned application Ser. No. 10/376,453, filed Feb. 26, 2003; all incorporated herein by this reference.
As mentioned above, ADPLL 10 implements loop filter 14 in the purely digital domain, for example by way of a software routine, stored at and executed by digital processor 11 (FIG. 1) along with its other functions. For example, if loop filter 14 is implemented by a software routine executed by digital processor 11, digital processor 11 would effectively compute each frequency control word FREQ from the current value of phase error word PH_ERR, according to a digital filter equation or routine.
An example of a first-order filter suitable for loop filter 14 according to the preferred embodiment of the invention, such a filter readily implementable by way of a software routine, may have a transfer function H(z) (in the z-domain) such as:
      H    ⁡          (      z      )        =            G      1        +                  G        2                    1        -                  z                      -            1                              In the conventional implementation of loop filter 14 in software, the gain values G1, G2 are simply stored in memory of digital processor 11.
By way of further background, various types of digital-controlled oscillators (DCOs) are known in the art. These DCO types range from a simple divide-by-N counter, in which a digital counter modulo-counts cycles of a fixed high-frequency oscillator output, with the modulo value selected by a digital frequency select word. Increment-decrement (ID) counters are the basis of another type of DCO, in which output clock edges are generated in response to carry and borrow signals from a loop filter, in combination with an input clock signal at a fixed high frequency. These and other conventional DCOs, as well as conventional phase-locked loops, typically depend upon the stability of the input clock signal. Accordingly, if significant jitter or noise is present on the input clock signal, this jitter and noise tends to couple to the output clock signal. This is of course undesirable. However, in many circuit applications, such as in video decoders, jitter and noise on the incoming clock signal cannot be avoided, and therefore it is difficult in such applications to digitally generate a stable and clean output clock signal.
Furthermore, conventional DCO and PLL circuits are typically not able to generate a stable and high-fidelity clock signal that has a frequency at a large multiple of the input clock signal. FIG. 4 illustrates a conventional PLL-based frequency multiplier. In this example, the input signal is at frequency fin, and is received at one input of conventional phase detector 32. Phase detector 32 generates a signal corresponding to the phase difference between the input signal and the feedback signal from divide-by-N frequency divider 38; this signal is filtered by loop filter 34, and then applied to VCO (or DCO, as the case may be) 36. VCO 36 then generates an output signal at frequency fout, which is also fed back to frequency divider 38 for generation of the feedback signal to phase detector 32. The feedback arrangement of this conventional PLL ensures that, in the steady-state, the phase error between the input signal and the output of frequency divider 38 tends to zero. In other words, VCO 36 is controlled so that its output signal at frequency fout locks to a frequency and phase such that the feedback signal from frequency divider 38, at frequency fout/N, is synchronized with the input signal at frequency fin. This forces the output clock signal frequency fout to the frequency fin*N.
It has been observed, however, that the maximum value of multiplier N that can still result in a stable output frequency fout is limited in this conventional architecture of FIG. 4. For example, if N is on the order of 1000 or greater, the rate at which phase-detector 32 updates the phase synchronization is quite low, on the order of 1000 or more cycles of the output clock signal at frequency fout. This slow update rate generally results in drift of the output frequency fout. Especially in applications, such as video decoders, that rely upon stable clock signal frequencies for high fidelity operation, significant frequency drift cannot be tolerated.